1. Field of the Invention
This invention relates to a semiconductor device in which a well is divided into a plurality of parts by a trench, and a method of manufacturing the semiconductor device.
2. Description of the Background Art
Semiconductor devices are usually formed by using a p-type semiconductor substrate (e.g., silicon substrate). As shown in FIG. 29, a p-channel transistor pT (source drain regions RN are of n-type) may be formed on a p-type semiconductor substrate 900, whereas in forming an n-channel transistor nT (source drain regions RP are of p-type), it is necessary to form a local n-type layer NW. The layer NW is called xe2x80x9cwell.xe2x80x9d
Wells are generally classified as thermal diffusion well and retro-grade well. In forming a thermal diffusion well NW, impurity N is implanted into a shallow position in a semiconductor substrate 900 (see FIG. 30), and the structure of FIG. 30 is subjected to heat treatment at high temperature for a prolonged time, so that the impurity N is diffused into the semiconductor substrate 900 (see FIG. 31), resulting in the thermal diffusion well NW. A retro-grade well MW is formed by implanting impurity N into a deep position in a semiconductor substrate 900, as shown in FIG. 32.
FIG. 33 shows the impurity concentration profile on the line Axe2x80x94A of FIG. 32. Since the retro-grade well is formed by implanting the impurity N, the impurity concentration profile can be set arbitrarily. In FIG. 33 it is controlled such that the impurity concentration has a maximum at a deep position P1 in the semiconductor substrate 900, and the impurity concentration at a shallow position P2 in the substrate 900 is higher than that of the substrate 900 and sufficiently lower than that of the channel. This offers the merit that the transistor nT in the well NW is protected against the influence of the potential outside of the well NW.
In recent years, the decreased size of a transistor nT has created the need for increasing the impurity concentration of the well NW in order to suppress punch through. In some elements, therefore, a well NW is intentionally distributed so as to reach the main surface of a semiconductor substrate 900 for adjustment of the impurity concentration of the well NW.
Adjustment of impurity concentration is required to not only an n-channel transistor nT but also a p-channel transistor pT in some cases. In this case, a p-type well PW is formed (see FIG. 34).
Further, if it is desired to arbitrarily set the substrate potential of the p-channel transistor pT (i.e., the potential of a back gate), the well PW is electrically isolated from other regions by an n-type bottom well BNW and a well NW, as shown in FIG. 35.
When a well NW and a well PW are in contact with each other (see FIG. 36), both wells can be electrically isolated by a depletion layer DR to be generated at the interface therebetween. This merit is to permit an easy electrical isolation between the well NW and the well PW. The depletion layer DR, however, has a tendency to extend and thus it might extend throughout a zone EUR. This causes the demerit that it is impossible to form a transistor in the zone EUR. An element isolation film Ta is formed in the zone EUR in which no transistor is formed (see FIG. 37).
To overcome the above demerit, a trench is formed at the boundary between the well NW and the well PW, and an element isolation film Tb is buried in the trench (see FIG. 38). Thereby, no depletion layer occurs at a well boundary between the well NW and the well PW (i.e., in the vicinity of the element isolation film Tb). This offers the merit that a transistor can be formed in the zone EUR by reducing the margin from the well boundary to a transistor. Unfortunately, the step of employing a trench is complicated and expensive which are the drawbacks of this step.
Two methods of well isolation using a trench are presently proposed. One comprises a first step of forming an element isolation film and a second step of forming n-type and p-type wells. FIG. 39 shows a structure formed by this method. With this method, no disadvantages are caused by reducing the margin from a well boundary to an element, however, the well isolation process using a trench involves the above two steps. Accordingly, this method is time-consuming and increases the manufacturing cost.
The other is to conduct the above first and second steps at the same time. FIG. 40 shows a structure formed by this method. The structure of FIG. 40 is realized by forming a deep element isolation film Th such as to correspond to the depth of wells NW and PW (see FIG. 41), or forming shallow wells NW and PW such as to correspond to the thickness of an element isolation film Th (see FIG. 42), alternatively, in a combination of these. In any event, the depth of the element isolation films Tb is evened and each of the wells NW and PW is divided into a plurality of parts by the element isolation film Tb.
It is, however, necessary to open a contact 201 per active region, namely, per well (see FIG. 43), in order to apply the desired potential to each of the isolated wells NW and PW. Thus it is necessary to increase the area of a well by the amount of a region CR for providing the contact 201. That is, as a whole, it fails to take full advantage of the merit in terms of area that is obtained by the trench as stated earlier with respect to FIG. 38. Also, there is a problem that layout area is increased by the amount of the region CR to be provided per well.
Accordingly, an object of the present invention is to provide a semiconductor device in which a well is divided into a plurality of parts by a trench, to effect a reduction in layout area, as well as a method of manufacturing the semiconductor device.
According to a first aspect of the present invention, a semiconductor device comprises: a semiconductor substrate; an element isolation film formed such as to have to a predetermined depth from a main surface of the semiconductor substrate, the element isolation film dividing the area from the main surface to the depth into a plurality of first regions; first wells formed in the first regions, respectively; and a second well formed in a second region deeper than the first wells in the semiconductor substrate, the second well being in contact with some of the first wells.
According to a second aspect, the semiconductor device according to the first aspect is characterized in that the first and second wells of the first and second regions on one side with reference to a predetermined boundary are of a first conductivity type, and the first and second wells on the other side are of a second conductivity type.
According to a third aspect, the semiconductor device according to the second aspect is characterized in that the second well of the first conductivity type and the second well of the second conductivity type are not in contact with each other.
According to a fourth aspect, the semiconductor device according to the first aspect is characterized in that the second well is formed on only one side of the second region with reference to a predetermined boundary.
According to a fifth aspect, the semiconductor device according to the fourth aspect is characterized in that the second well is formed in a memory cell part in the second region.
According to a sixth aspect, the semiconductor device according to the first aspect is characterized in that the second well is formed only in the vicinity of the bottom of the element isolation film in the second region.
According to a seventh aspect, the semiconductor device according to the first aspect is characterized in that each impurity concentration of the first and second wells is higher as being closer to a boundary part between the first and second regions.
According to an eighth aspect, the semiconductor device according to the first aspect further comprises a third well formed in a third region deeper than the second region in the semiconductor substrate.
According to a ninth aspect, a method of manufacturing a semiconductor device comprises the steps of: (a) forming an element isolation film such as to have a predetermined depth from a main surface of a semiconductor substrate, to divide the area from the main surface to the depth into a plurality of first regions; and (b) forming first wells in the first regions, respectively, and forming a second well making contact with some of the first wells, in a second region deeper than the first wells in the semiconductor substrate.
According to a tenth aspect, the method according to the ninth aspect is characterized in that the step (b) comprises the steps of (b-1) covering, with a first resist, one side region of the main surface with reference to a predetermined boundary in the semiconductor substrate; (b-2) implanting impurity of a first conductivity type into the first region by using the first resist as a mask; (b-3) implanting impurity of the first conductivity type into the second region by using the first resist as a mask; (b-4) removing the first resist; (b-5) covering, with a second resist, the other side region of the main surface with reference to the boundary in the semiconductor substrate; (b-6) implanting impurity of a second conductivity type into the first region by using the second resist as a mask; (b-7) implanting impurity of the second conductivity type into the second region by using the second resist as a mask; and (b-8) removing the second resist.
According to an eleventh aspect, the method according to the ninth aspect is characterized in that the step (b) comprises the steps of: (b-1) covering, with a first resist, one side region of the main surface with reference to a predetermined boundary in the semiconductor substrate; (b-2) implanting impurity of a first conductivity type into the first region by using the first resist as a mask; (b-3) reforming the first resist such as to be thicker, as a second resist; (b-4) implanting impurity of the first conductivity type into the second region by using the second resist as a mask; (b-5) removing the second resist; (b-6) covering, with a third resist, the other side region of the main surface with reference to the boundary in the semiconductor substrate; (b-7) implanting impurity of a second conductivity type into the first region by using the third resist as a mask; (b-8) reforming the third resist such as to be thicker, as a fourth resist; (b-9) implanting impurity of the second conductivity type into the second region by using the fourth resist as a mask; and (b-10) removing the fourth resist.
According to a twelfth aspect, a method of manufacturing a semiconductor device comprises the steps of: (a) forming a trench such as to have a predetermined depth from a main surface of a semiconductor substrate, to divide the area from the main surface to the depth into a plurality of regions in the semiconductor substrate; (b) implanting a first impurity from above the main surface into the trench; and (c) implanting a second impurity from above the main surface into the regions.
The first aspect enables that some of the first wells are electrically connected one another through the second well. It is therefore possible to apply a potential to all the first wells by placing a contact in at least one of the first wells. This leads to a reduction in layout area.
The second aspect allows the electrical connection between the first and second wells to be performed each conductivity type separately.
The third aspect has no chance that a depletion layer extends from the third region in the second region to the first well because the second well of the first conductivity type and the second well of the second conductivity type are not in contact with each other.
The fourth aspect enables to simplify the process and reduce the manufacturing cost, as compared with a semiconductor device of the second aspect.
The fifth aspect is extremely effective when applied to the memory cell part alone, in terms of simplification in process, manufacturing cost reduction and layout area reduction.
The sixth aspect enables to form the second well by utilizing a trench, for example.
The seventh aspect enables to prevent a depletion layer from extending to the first well even if the depletion layer occurs in the second well, by setting the impurity concentration of the first and second wells at the boundary between the first and second regions, to a sufficiently large value.
The eighth aspect allows the potential of the first and second wells to be set independently of the potential at a position lower than the third well.
The ninth aspect enables to manufacture a semiconductor device of the first aspect, and simplify the step of providing a contact and the step of providing wiring connected to the contact because the contact may be provided at least one of the first wells.
The tenth aspect enables to manufacture a semiconductor device of the second aspect, and simplify the manufacturing steps because a single resist is used in impurity implantation into both first and second regions.
The eleventh aspect enables to manufacture a semiconductor device of the third aspect, and easily obtain the structure in which the second well of the first conductivity type and the second well of the second conductivity type are not in contact with each other, by utilizing the feature that the taper of a resist becomes significant when the resist is thickened. In addition, even if impurity lift phenomenon occurs due to a marked taper of the second and fourth resists, the impurity related to the lift phenomenon is to be contained in the first well, thereby suppressing a noticeable change in impurity concentration profile.
The twelfth aspect enables to manufacture a semiconductor device of the sixth aspect, and form the second well by utilizing a trench.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.